ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF516/BF518 (F)

Preliminary Technical Data

JTAG Test And Emulation Port Timing

Table 43 and Figure 32 describe JTAG port operations.

Table 43. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Parameters

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

System Inputs Setup Before TCK High1

tHSYS

System Inputs Hold After TCK High1

tTRSTW

TRST Pulse Width2 (measured in TCK cycles)

Switching Characteristics

20

ns

4

ns

4

ns

4

ns

5

ns

4

TCK

tDTDO

tDSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low3

10

ns

0

12

ns

1 System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TCK, TD1, TMS, TRST, RESET, NMI,

BMODE2–0.

2 50 MHz Maximum

3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,

DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO, TD0, EMU.

TCK

tTCK

TMS

TDI

TDO

tSTAP

tHTAP

tDTDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSSYS

tHSYS

tDSYS

Figure 32. JTAG Port Timing

Rev. PrE | Page 48 of 62 | March 2009

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