ADSP-BF512/BF514/BF516/BF518 (F)
Preliminary Technical Data
MII TxCLK
ETxD3-0
ETxEN
ERxCLK
tETXCLKW
tETXCLK
tETXCLKOH
tETXCLKOV
Figure 27. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
tREFCLKW
tR EF CL K
ERxD1-0
ERxDV
ERxER
tERXCLKIS
tERXCLKIH
Figure 28. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
RMII REF_CLK
ETxD1-0
ETxEN
tREFC LK
tEREFCLKOH
tEREFCLKOV
Figure 29. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
MII CRS, COL
tECRSH
tECOLH
tECRSL
tECOLL
Figure 30. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
Rev. PrE | Page 46 of 62 | March 2009