ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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Preliminary Technical Data
ADSP-BF512/BF514/BF516/BF518 (F)
Table 39. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter1
tEREFCLKF
REF_CLK Frequency (fSCLK = SCLK Frequency)
tEREFCLKW
EREF_CLK Width (tEREFCLK = EREFCLK Period)
tEREFCLKIS
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
tEREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Min
None
tEREFCLK x 35%
4
2
Max
50 MHz + 1%
2 x fSCLK + 1%
tEREFCLK x 65%
Unit
ns
ns
ns
ns
Table 40. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter1
tEREFCLKOV
tEREFCLKOH
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
Min
Max
Unit
8.1
ns
2
ns
Table 41. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2
Min
Max
Unit
tECOLH
tECOLL
tECRSH
tECRSL
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
tETxCLK x 1.5
ns
tERxCLK x 1.5
tETxCLK x 1.5
ns
tERxCLK x 1.5
tETxCLK x 1.5
ns
tETxCLK x 1.5
ns
1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 42. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1
Min
Max
Unit
tMDIOS
tMDCIH
tMDCOV
tMDCOH
MDIO Input Valid to MDC Rising Edge (Setup)
MDC Rising Edge to MDIO Input Invalid (Hold)
MDC Falling Edge to MDIO Output Valid
MDC Falling Edge to MDIO Output Invalid (Hold)
11.5
ns
11.5
ns
25
ns
–1
ns
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
ERxCLK
tERXCLKW
tERXC LK
ERxD3-0
ERxDV
ERxER
tERXCLKIS
tERXCLKIH
Figure 26. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Rev. PrE | Page 45 of 62 | March 2009
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