ADSP-BF518KSWZ-ENG View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF518KSWZ-ENG Datasheet PDF : 62 Pages
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ADSP-BF512/BF514/BF516/BF518 (F)
Preliminary Technical Data
Up/Down Counter/Rotary Encoder Timing
Table 36. Up/Down Counter/Rotary Encoder Timing
Parameter
VDDEXT = 1.8 V
Min Max
Timing Requirements
tWCOUNT
tCIS
tCIH
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low1
Counter Input Hold Time After CLKOUT Low1
tSCLK + 1
4.0
4.0
1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
VDDEXT = 2.5/3.3 V
Min Max Unit
tSCLK + 1
ns
4.0
ns
4.0
ns
CLK OUT
CUD/CDG/CZM
tCIS
tCIH
tWCOUNT
Figure 25. Up/Down Counter/Rotary Encoder Timing
10/100 Ethernet MAC Controller Timing
Table 37 through Table 42 and Figure 26 through Figure 31
describe the 10/100 Ethernet MAC Controller operations.
Table 37. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter1
tERXCLKF
ERxCLK Frequency (fSCLK = SCLK Frequency)
Min
None
tERXCLKW
ERxCLK Width (tERxCLK = ERxCLK Period)
tERXCLKIS
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
tERXCLKIH
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
tERxCLK x 35%
7.5
7.5
Table 38. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter1
tETF
ETxCLK Frequency (fSCLK = SCLK Frequency)
Min
None
tETXCLKW
ETxCLK Width (tETxCLK = ETxCLK Period)
tETXCLKOV
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
tETXCLKOH
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
1 MII outputs synchronous to ETxCLK are ETxD3–0.
tETxCLK x 35%
0
Max
25 MHz + 1%
fSCLK + 1%
tERxCLK x 65%
Max
25 MHz + 1%
fSCLK + 1%
tETxCLK x 65%
20
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Rev. PrE | Page 44 of 62 | March 2009
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