STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VIII - INTERNAL REGISTERS (continued)

VIII.12 - Time Slot Assigner Data Register - TADR (16)H

bit15

bit8 bit7

V11 V10 V9 V8 V7 V6 V5 V4 V3 V2

After reset (0000)H

bit 0

V1 CH4 CH3 CH2 CH1 CH0

CH0/4 : CHANNEL0/4

These five bits define one of 32 channels associated to TIME SLOT defined by the previous

Register (TAAR).

V1/8 : VALIDATION

The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit

V9 : VALIDATION SUBCHANNEL

V 9 = 1, each V1/8 bit is taken into account once every 250ms.

In transmit direction, data is transmitted consecutively during the time slot of the current frame

and during the same time slot of the next frame.Id est.: the same data is transmitted in two

consecutive frames.

In receive direction, HDLC controller fetches data during the time slot of the current frame and

ignores data during the same time slot of the next frame.

V 9 = 0, each V1/8 bit is taken into account once every 125ms.

V10 : DIRECT MHDLC ACCESS

If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time

slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC

Controller.

If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the

current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same

current time slot.

N.B : If D7 = 1, (see ”General Configuration Register GCR (02)H”) the Tx HDLC controller is

connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.

DOUT0 to DOUT7).

V11 : VALIDATION of CB pin

This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register).

if CSMA = 0 :

V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into

account.

V11 = 0, ContentionBus pin is high impedance during the current time slot (This pin is an open

drain output).

VIII.13 - HDLC Transmit Command Register - HTCR (18)H

bit15

bit8 bit7

CH4 CH3 CH2 CH1 CH0 READ Nu CF PEN CSMA NCRC F

After reset (0000)H

bit 0

P1 P0 C1 C0

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels.

62/83

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