STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VIII - INTERNAL REGISTERS (continued)

C1/C0 : COMMAND BITS

C1 C0

Commands Bits

0 0 ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven ”1”

immediately, afterwards HDLC Controller transmits ”1” or flag in accordance with F bit, generates

an interrupt and waits new command such as START orn CONTINUE.

If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and

waits a new command such as START or CONTINUE.

0 1 START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial

descriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

1 0 CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already transmitted.

1 1 HALT ; after transmitting frame, HDLC Controller transmits ”1” or flag in accordance with F bit,

generates an interrupt and is waiting new command such as START or CONTINUE.

P0/1

: PROTOCOL BITS

P1 P0

Transmission Mode

0 0 HDLC

0 1 Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.

1 0 Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.

1 1 Reserved

F

: Flag

F = 1 ; flags are transmitted betweenclosing flag of currentframe and opening flag of next frame.

F = 0 ; ”1” are transmitted between closing flag of current frame and opening flag of next frame.

NCRC : CRC NOT TRANSMITTED

NCRC = 1, the CRC is not transmitted at the end of the frame.

NCR C =0, the CRC is transmitted at the end of the frame.

CSMA : Carrier Sense Multiple Access with Contention Resolution

CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission

by the Tx HDLC.

CSMA = 0, CB output and the Echo Bit are defined by V11 (see ” Time slot Assigner Data

Register TADR (16)H”).

PEN : CSMA PENALTY significant if CSMA = 1

PEN = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count

(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the buffer descriptor related to the frame.

PEN = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count

(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8

or 10 given by the transmit descriptor related to the frame).

CF : Common flag

CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next

frame is ready to be transmitted.

CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.

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