STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VIII - INTERNAL REGISTERS (continued)

VIII.14 - HDLC Receive Command Register - HRCR (1A)H

bit15

bit8 bit7

bit 0

CH4 CH3 CH2 CH1 CH0 READ AR21 AR20 AR11 AR10 CRC Nu P1 P0 C1 C0

After reset (0000)H

READ : READ COMMAND MEMORY

READ = 1, READ COMMAND MEMORY.

READ = 0, WRITE COMMAND MEMORY.

CH0/4 : These five bits define one of 32 channels.

C1/C0 : COMMAND

C1 C0

Commands Bits

0 0 ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the

reception, generates an interrupt and waits new command such as START orn CONTINUE.

If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits

a new command such as START or CONTINUE.

0 1 START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial

descriptor. The initial descriptor address is provided by the Initiate Block located in external

memory.

1 0 CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next

descriptor. The next descriptor address is provided by the previous descriptor from which the

related frame had been already received.

1 1 HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and

waits a new command such as START or CONTINUE.

P0/1

: PROTOCOL BITS

P1 P0

Transmission Mode

0 0 HDLC

0 1 Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.

1 0 Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.

1 1 Reserved

CRC : CRC stored in external memory

CRC = 1, the CRC is stored at the end of the frame in external memory.

CRC = 0, the CRC is not stored into external memory.

AR10 : Address Recognition10

AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR.

If the first byte received and AF0/7 bits are not identical the frame is ignored.

AR10 = 0, First byte after openingflag of receivedframe is not compared to AF0/7 bits of AFRDR

Register.

AR11 : Address Recognition 11

AR11 = 1, First byte after opening flag of received frame is compared to all ”1”s.If the first byte

received is not all ”1”s the frame is ignored.

AR11 = 0, First byte after opening flag of received frame is not compared to all ”1”s.

AR20 : Address Recognition 20

AR20 = 1, Secondbyte after opening flag of receivedframe is comparedto AF8/15bits of AFRDR

Register. If the second byte received and AF8/15 bits are not identical the frame is ignored.

AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of

AFRDR Register.

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