VII - MICROPROCESSOR TIMING (continued)
Figure 40 : 80C186 Write Cycle
NCS0/1
t1
t2
READY
t3
NAS/ALE
t4
NDS/NRD
t12
t8
t5
t6
AD0/15
A0/15
D0/15
STLC5464
R/W / NWR
NBHE A16/19
t7
t9
t10
NBHE
A16/19
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Parameter
Delay Ready / Chip Select (if t3 > t1), (30pF)
Hold Time Chip Select / NWR
Delay Ready / ALE (if t1 > t3), (30pF)
Width ALE
Set-up Time Address / ALE
Hold Time Address / ALE
Set-up Time Data / NWR
Hold Time Data / NWR
Set-up Time NBHE-Address A16/19 / ALE
Hold Time Address 16/19 / ALE
Hold Time NBHE- / NWR
Delay NWR / NCS
t11
NBHE
Min.
0
10
0
20
5
5
-15
15
5
10
10
0
Typ.
Max.
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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