STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VIII - INTERNAL REGISTERS (continued)

VIII.9 - Connection Memory Address Register - CMAR (10)H

ACCESS MODE REGISTER (AMR)

DESTINATION REGISTER (DSTR)

bit15

bit8 bit7

bit 0

Nu Nu TC CACL CAC Nu CM READ OM2 OM1 OM0 OTS4 OTS3 OTS2 OTS1 OTS0

After reset (0800)H

This 16 bit register is constitutedby two registers : DESTINATIONREGISTER (DSTR) and ACCESSMODE

REGISTER (AMR) respectively 8 bits and 6 bits.

Remark : It is mandatory for this specific register to write successively :

- first DSTR

- then AMR

DESTINATION REGISTER (DSTR)

When DSTR Register is written by the microprocessor, a memory access is launched. DSTR has two use

modes depending on CM (bit of CMAR).

CM = 1, access to connection memory (read or write) ;

When CM = 1, OTS 0/4 and OM 0/2 bits are defined hereafter :

OTS 0/4 : Output time slot 0/4 define OTSy with : 0 ≤ y ≤ 31,

OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with : 0 ≤ q ≤ 7.

- CAC = CACL = 0, DSTR is the Address Register of the Connection Memory;

- CAC or CACL = 1, DSTR is used to indicate the current address for the Connection Memory ; its contents

is assigned to the outputs.

CM = 0, access to data memory (read only) ;

- DSTR is the Address Register of the Data Memory; its contents is assigned to the inputs.

ACCESS MODE REGISTER (AMR)

READ : READ MEMORY

READ = 1, Read Connection Memory (or Data Memory in accordance with CM).

READ = 0, Write Connection Memory.

CM : CONNECTION MEMORY

CM = 1, Write or Read Connection Memory in accordance with READ.

CM = 0, Read only Data Memory (READ = 0 has no effect).

CAC : CYCLICAL ACCESS

CAC = 1

if Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 256 locations of ConnectionMemory occurs. The first address is indicated by the

register DSTR, the last is (FF)H.

if Read Connection Memory, an automatic transfer of data from the location indicated by the

register (DSTR) into Connection Memory Data Register (CMDR) after reading by the

microprocessor occurs. The last location is (FF)H.

CAC = 0, Write and Read Connection Memory in the normal way.

CACL : CYCLICAL ACCESS LIMITED

CACL = 1

If Write Connection Memory, an automatic data write from Connection Memory Data Register

(CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS

0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location

is q +1 F(H).

If Read Connection Memory, an automatic transfer of data from Connection Memory into

Connection Memory Data Register (CMDR) after reading this last by the microprocessor

occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq

as defined by OM0/2. The last location is q +1 F(H).

CACL = 0, Write and Read Connection Memory in the normal way.

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