STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VIII - INTERNAL REGISTERS (continued)

ME : MESSAGE ENABLE

ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously.

ME = 0 The contents of Connection Memory acts as an address for the Data Memory.

Nu : Not used.

VIII.8 - Connection Memory Data Register - CMDR (0E)H

CONTROL REGISTER (CTLR)

SOURCE REGISTER (SRCR)

bit15

bit8 bit7

bit 0

Nu PS PRSA PRSG INS OTSV LOOP SI IM2 IM1 IM0 ITS 4 ITS 3 ITS 2 ITS 1 ITS 0

After reset (0000)H

This 16 bit register is constituted by two registers :

SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR) respectively 8 bits and 7 bits.

SOURCE REGISTER (SRCR) has two use modes depending on CM (part of CMAR).

CM = 1, access to connection memory (read or write)

- PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter :

ITS 0/4 : Input time slot 0/4 define ITSx with : 0 ≤ x ≤ 31;

IM0/2 : Input Time Division Multiplex 0/2 define ITDMp with : 0 ≤ p ≤ 7.

- PRSG = 1, the Pseudo Random Sequence Generator is validated, SRCR is not significant.

CM = 0, access to data memory (read only). SRC is the data register of the data memory.

CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multi-

plex OTDMq :

SI : SEQUENCE INTEGRITY

SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy(constant delay).

SI = 0, the delay is minimum to pass through the data memory (variable delay).

LOOP : LOOPBACK per channelrelevant if two connectionshas been established (bidirectional or not).

LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq.

OTSV = 1, transparentMode LOOPBACK.

OTSV = 0, not Transparent Mode LOOPBACK.

OTSV : OUTPUT TIME SLOT VALIDATED

OTSV = 1, OTSy OTDMq is enabled.

OTSV = 0, OTSy OTDMq is High Impedance.

(OTSy : Output Time slot with 0 ≤ y ≤ 31; OTDMq : Output Time Division Multiplex with 0 ≤ q ≤ 7).

INS : INSERT

INS = 1 The transfer from PRS Generator or Connection Memory to DOUT0/7 is validated.

INS = 0 The transfer from Data Memory to DOUT0/7 is validated.

PRSG : Pseudo Random Sequence Generator

This bit has effect only if INS = 1.

If PRSG = 1, Pseudo Random Sequence Generator delivers eight bits belonging to the same

Sequence. Hyperchannel at n x 64 Kb/s is possible.

If PRSG = 0, Connection Memory delivers eight bits D0/7.

PRSA : Pseudo Random Sequence analyzer

If PRSA = 1, PRS analyzer is enabled during OTSy OTDMq and receives data :

INS = 0, data comes from Data Memory.

INS = 1 AND PRSG=1, Data comes from PRS Generator (Test Mode).

If PRSA = 0, PRS analyzer is disabled during OTSy OTDMq.

PS : Programmable Synchronization

If PS = 1, Programmable Synchronization Signal Pin is at ”1” during the bit time defined by OTSy

and OTDMq.

For OTSy and OTDMq with y = q = 0, PSS pin is at ”1” during the first bit of the frame defined

by the Frame synchronization Signal (FS).

If PS = 0, PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq.

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