STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
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STLC5464
VII - MICROPROCESSOR TIMING (continued)
VII.4 - 68000 MOD0=0, MOD1=0, MOD2=1
Figure 41 : 68000 Read Cycle
NCS0/1
t1
NDTACK
t3
t12
NAS/ALE
SIZE0/NLDS
SIZE1/NUDS
A1/23
R/W / NWR
D0/15
t5
A1/23
t7
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t12
Parameter
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
Hold Time Chip Select / NLDS-NUDS
Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
Delay NDTACK / NLDS-NUDS Rising Edge
Set-up Time Address / NAS
Hold Time Address / NLDS-NUDS
Data Valid before NDTACK Falling Edge (30pF)
Data Valid after NLDS-NUDS Rising Edge (30pF)
Delay NDS / NCS
t2
t4
t6
t8
Min.
0
14
0
0
9
9
0
0
0
Typ.
Max.
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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