STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
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STLC5464
VIII - INTERNAL REGISTERS (continued)
AR21 : Address Recognition 21
AR21 = 1, Second byte after opening flag of received frame is compared to all ”1”s. If the
Second byte received is not all ”1”s the frame is ignored.
AR21 = 0, Second byte after opening flag of received frame is not compared to all ”1”s.
Second Byte
AR21 AR20
0
0
0
0
0
0
0
0
First Byte
AR11 AR10
0
0
0
1
1
0
1
1
Conditions to Receive a Frame
Each frame is received without condition.
Only value of the first received byte must be equal to that of AF0/7 bits.
Only value of the first received byte must be equal to all ”1”s.
The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s.
0
1
0
0 Only value of the second received byte must be equal to that of AF8/15 bits.
0
1
0
1 The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to that of AF8/15 bits.
0
1
1
0 The value of first received byte is must be equal to all ”1”s and the value of
second received byte must be equal to that of AF8/15 bits.
0
1
1
1 The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s and the value of the second received byte must be equal to that
of AF8/15 bits.
1
0
0
0 Only the value of the second received byte must be equal to all ”1”s.
1
0
0
1 The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to all ”1”s.
1
0
1
0 The value of the first received byte must be equal to all ”1”s and the value of
the second received byte must be equal to ”1” also.
1
0
1
1 The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal to all ”1”s.
1
1
0
0 The value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
1
1
0
1 The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
1
1
1
0 The value of the first received byte must be equal to ”1” and the value of the
second received byte must be equal either to that of AF8/15 or to all ”1”s.
1
1
1
1 The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal either to that
of AF8/15 or to all ”1”s.
VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H
bit15
bit8 bit7
bit 0
CH4 CH3 CH2 CH1 CHO READ Nu Nu r
e
s
e
r
v
e
d
After reset (0000)H
The write operation is lauched when AFRAR is written by the microprocessor.
READ : READ ADDRESS FIELD RECOGNITION MEMORY
READ=1, READ AFR MEMORY.
READ=0, WRITE AFR MEMORY.
CH0/4 : These five bits define one of 32 channels in reception
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