CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

LA[28:0]

DRAM Address

t1 a

MEMCLK

D[31:0]

Address + 4 Address + 8

t1 a

td s _ d r a m

td h _ d r a m

nRAS[x]

nCAS[3:0]

tr a s l

tc a s l

tc a s h

tr p

tr a s h

tc a c

RA[11:0]

tr a 1

Row Address

tr a 2

Column Address

tc a l

Column Address + 1 Column Address + 2

tc a h

Figure 22-7. Fast Page Mode DRAM Read Timing (32 Bit)

LA[28:0]

MEMCLK

DRAM Address

Address + 4

Address + 8

D[31:0]

nRAS[x]

nCAS[3:0]

RA[11:0]

nWE

td a 1

tr a s l

Row Address

tr a 1

td a 2

td a 2

tw d h

tr a s h

tc a s l

tc a s h tc a s 2 l

tc a s 2 h

Column Address Column Address + 1 Column Address + 2

tc a l

tc a h

tn w e l

tn w e h

Figure 22-8. Fast Page Mode DRAM Write Timing (32 Bit)

206

ELECTRICAL SPECIFICATIONS

ADVANCE DATA BOOK v2.0

June 1997

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