CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

Table 22-5. DRAM Memory Refresh Timing

Symbol

trref1

trref2

tcrefl

tcrefh

trarf

Parameter

MEMCLK rising to nRAS

MEMCLK falling to nRAS

MEMCLK rising to nCAS[3:0] falling

MEMCLK rising to nCAS[3:0] rising

MEMCLK rising to RA[11:0] changing

CL-PS7500FE

System-on-a-Chip for Internet Appliance

40 MHz

MIN

MAX

12

11

16

16

22

56 MHz

MIN MAX

12

11

16

16

22

Units

ns

ns

ns

ns

ns

LA[28:0]

MEMCLK

nRAS[0]

nRAS[1]

nRAS[2]

nRAS[3]

nCAS[3:0]

RA[11:0]

Address for next instruction

tr r e ß

tr r e f 2

0xF

0x0

tc r e ß

xxx

xxx

tr a r f

tr r e f 1

tr r e f 2

0xF

tc r e f h

xxx

tr a r f

tr a r f

Figure 22-11. DRAM Memory Refresh Timing

208

ELECTRICAL SPECIFICATIONS

ADVANCE DATA BOOK v2.0

June 1997

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