CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
LA[28:0]
MEMCLK
D[31:0]
DRAM Address
t1 a
Address + 4 Address + 8
t1 a
Word 1
td s _ d r a m
td h _ d r a m
Word 2
Word 3
nRAS[x]
nCAS[3:0]
tr a s l
tc a s l
tc a s h
tr a s h
tc a c
RA[11:0]
tr a 1
Row Address
tr a 2
Column Address
tc a l
Column Address + 1 Column Address + 2
tc a h
Figure 22-9. EDO DRAM Read Timing (32 Bit)
LA[28:0]
MEMCLK
DRAM Address
D[31:0]
nRAS[x]
nCAS[3:0]
RA[11:0]
nWE
td a l
tr a s l
tw d h
tr p
tr a s h
Row Address
tr a 1
tc a s l tc a s h
Column Address
tc a l
tn w e l
tc a h
tn w e h
Figure 22-10. EDO DRAM Write Timing — Single Word
June 1997
ADVANCE DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
207
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