ADE3700XT 查看數據表（PDF） - STMicroelectronics
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ADE3700XT Datasheet PDF : 89 Pages
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Output Multiplexer
ADE3700
2.19
Output Multiplexer
The Output Multiplexer formats the single wide data stream from the output of the APC block into a
single or double wide data path for the flat panel. The architecture is shown in Figure 10.
Figure 10: Output Mux Block Diagram
rin[7:0] 8
gin[7:0] 8
Right
Shift
Right
Shift
8 Byte
Flip
8 Byte
Flip
8
Red &
8 Blue
Swap
24 Single to
Double Wide
Converter
48
Data
Inversion
bin[7:0] 8
Right
8 Byte
8
Shift
Flip
enab_in
hsync_in
vsync_in
tcon_in[13:0]
14
pwm_a_in
pwm_b_in 2
tci[13:0]
48
2
hclk
rda[7:0]
gda[7:0]
bda[7:0]
rdb[7:0]
gdb[7:0]
bdb[7:0]
inv_a
inv_b
Output Mux/Reg
FLOPS
RSDS Logic and Per Pin Delay
8
48
3
tcon_out[7:0]
routa[7:0]
gouta[7:0]
bouta[7:0]
routb[7:0]
goutb[7:0]
boutb[7:0]
enab_out clk_out
hsync_out
vsync_out
Latency is not important, as long as the timing relationship between hsync, vsync, enab and data is
preserved at the output. In Double Wide mode, the first pixel must be properly aligned even if the
number of pixels in blanking or active are odd. The divide-by-2 circuit can be set to resync per line
(based on data_enab and hsync_in edge) and per frame (based on vsync_in edge). The most
reliable timing is when hsync and vsync are in the “low” counts of the timing core counters (i.e.
hsync_set and hsync_rst are both below the active data region start/end counts). In the event that
hsync and vsync are in the “high” (after active region) counts, the device should be set to sync to
data_enab_re.
The Per Pin Delay and RSDS logic occur after the last latch and are implemented on all channels to
maintain delay balance between signals that go into RSDS mode (data and clk/hsync) and those
that do not (de/vsync and tcon).
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