ADE3700XT 查看數據表（PDF） - STMicroelectronics

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ADE3700XT

Analog LCD Display Engine for XGA and SXGA Resolutions

STMicroelectronics 

Pulse Width Modulation (PWM)

ADE3700

Table 32: Output Mux Registers (Sheet 4 of 4)

Register Name

OMUX_CTRL_3

OMUX_REFCOUNT

Addr

0x0C51

0x0C52

Mode Bits

R/W

[7:3]

R/W

[2]

R/W

[1]

R/W

[0]

[7:6]

R

[5:0]

Default

Description

Reserved

0x0

PWM mux mode

0x0

PWM enable

0x0

TCON data invert enable, with computed

data invert pin.

Reserved

0x0

Returns a value that indicates the ADE

gate speed -- a function of temp and

voltage

higher = faster logic

2.20

Pulse Width Modulation (PWM)

The PWM block generates two signals that can be used to control backlight inverter switching

power components directly. It is derived from XCLK and can be powered up independently of the

DOTCLK and INCLK domains. The frequency, duty cycle, polarity and overlap/non-overlap are

programmable. The output frequency can be free-running or locked to the output vsync signal.

Table 33: PWM Registers (Sheet 1 of 2)

Register Name

PWM_CTRL0

Addr

0x01A0

Mode Bits Default

Description

R

[7] 0x0

PWM status

0: unlocked

1: locked

R/W

[6] 0x0

R/W

[5] 0x0

R/W

[4] 0x0

R/W

[3] 0x0

R/W

[2] 0x0

R/W

[1] 0x0

R/W

[0] 0x0

0: lock to CYCLES_PER_FRAME from the

free-running state machine

1: lock to CYCLES_PER_FRAME register

setting

PWM_A polarity

0: active low

1: active high

PWM_B polarity

0: active low

1: active high

0: normal operation

1: force PWM outputs to polarity settings

0: change period or duty cycle at the end of

the current cycle

1: smooth change, period or duty cycle

increment/decrement every

PWM_STEP_DELAY cycle

0: free-running

1: lock to out_vsync

0: disable PWM output

1: enable PWM output

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