ADE3700XT 查看數據表（PDF） - STMicroelectronics

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ADE3700XT

Analog LCD Display Engine for XGA and SXGA Resolutions

STMicroelectronics 

Output Multiplexer

Table 29: Sync Mux Specification

ADE3700

enable data

OUT_MUX_CTRL0[0]

0

1

enable tcon

OUT_MUX_CTRL1[3]

0

0

ENAB_OUT

HSYNC_OUT

VSYNC_OUT

0

ENI

0

HSI

0

VSI

eni = enab_in, hsi = hsync_in, vsi = vsync_in.

Table 30: TCON Mux Specification

1

1

INV_A

TCI_GATED_CLK

INV_B

enable tcon

OUT_MUX_CTRL1[3]

X

X

0

enable PWM

OUT_MUX_CTRL3[1]

0

1

1

PWM mux mode

OUT_MUX_CTRL3[2]

X

0

1

TCON_OUT7

TCON_OUT6

TCON_OUT5

TCON_OUT4

TCON_OUT3

TCON_OUT2

TCON_OUT1

TCON_OUT0

TCI7

TCI6

TCI5

TCI4

TCI3

TCI2

TCI1

TCI0

TCI7

TCI6

TCI5

TCI4

TCI3

TCI2

PWM_A

PWM_B

TCI7

TCI6

TCI5

TCI4

TCI3

TCI2

TCI1

TCI0

2.19.2 RSDS

In RSDS mode, clk and hsync outputs are the differential clock pair. All 48 data ports are combined

into neighboring pairs (e.g. orb0 and orb1 are differential pairs in RSDS mode). the lower index is

the positive sense differential output. TCON, data_enab and vsync outputs are unchanged.

data_enab and vsync can be used to output LVCMOS data inversion signals independent of RSDS

mode.

The following table indicates the pin, timing and data relationships in RSDS mode.

Table 31: RSDS Mode Specifications

RSDS Time

t

t+1

clk_o

0

1

hsync_o o[r,g,b][a,b](2n)

1

bit from 2n

0

bit from 2n+1

o[r,g,b][a,b](2n+1)

!bit from 2n

!bit from 2n+1

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