CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

2. ASTCR I/O Cycle Type and Hold Times

NOTE: This assumes Divide-by-1 mode for the clocks, MEMCLK and I_OCLK.

When ASTCR is low (reset value):

I/O cycle type

Simple I/O

Module I/O

PC style I/O

When ASTCR is high:

I/O cycle type

Simple I/O

Module I/O

PC style I/O

Minimum hold time

2 MEMCLK periods − 1 I_OCLK period

2 MEMCLK periods − 1.5 I_OCLK periods

2 MEMCLK periods − 1.5 I_OCLK periods

Minimum hold time

2 MEMCLK periods − 0.5 I_OCLK periods

2 MEMCLK periods − 0.5 I_OCLK periods

2 MEMCLK periods − 0.5 I_OCLK periods

3. Example

In a system with:

q I_OCLK = 32 MHz

q MEMCLK = 40 MHz

the minimum hold time for a PC-style access is:

q 3.125 ns, if ASTCR = 0

q 34.375 ns, if ASTCR = 1

In addition there is a small amount of extra hold time, due to the delay from the internal memory clock, to

the latch enable signal for the address.

NOTE: These times refer to the signals changes at the pad on the inside of the CL-PS7500FE. The relative capac-

itive loading of the latched address and I/O chip select determines the overall timing.

June 1997

ADVANCE DATA BOOK v2.0

233

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