CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1101

XXXXXXXX XXXXXXXX

Figure E-2. Frequency Synthesizer Register

These bits are only programmed during test and at reset (see Section 4 on page 240).

The internal IOCK32 signal derived from the I_OCLK input, provides a reference clock that is recom-

mended to be 32 MHz. The VCLKI input is driven from the output of the VCO, then this is selected as the

pixel clock.

The VCO is driven by the CL-PS7500FE PCOMP output, for most of the time is at the tristate value. When

the VCO frequency must be increased, PCOMP goes high, and vice-versa when the frequency must be

decreased.

The PCOMP output requires a filter before applying to the VCO. The user must select the filter and VCO.

A very simple and effective system can be built using an 74AC04 inverter pack, and a simple LC filter. The

filtered VCO output controls the operating voltage of the 74AC04 device. This system is shown in

Figure E-3, and has wide range of frequencies (LF to hundreds of MHz).

Since the output of this VCO is AC-coupled, VCLKI must be biased at the mid-voltage point. To do this,

connect a large resistor between VCLKI and VCLKO (VCLKO is the inversion of VCLKI).

NOTE: Low-power systems may require more complex circuitry to avoid DC paths during SUSPEND or STOP

modes.

238

June 1997

ADVANCE DATA BOOK v2.0

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