CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Appendix E

E.CL-PS7500FE Video Clock Sources

1. Introduction

To facilitate the high-resolution screen modes that the CL-PS7500FE can produce, apply a suitable

high-frequency clock. As the screen mode changes, the pixel rate must also change. This can be done:

q through the various clock inputs

q by the on-chip prescaler

q using an external voltage controlled oscillator, combined with the on-chip phase comparator, to form a PLL.

It is intended that most systems be built with a PLL system. The required circuitry is simple and allows a

high degree of flexibility. The advantages are that all the necessary clock frequencies can be derived from

one circuit, eliminating the need for multiple on-board crystals and clock-switching circuitry.

2. Clock Sources

CL-PS7500FE has three primary inputs for its pixel clock:

q HCLK

q VCLKI

q RCLK (this is the internal 32-MHz IOCK32 derived from I_OCLK)

VCLKI and the internal I_OCLK32 (derived from I_OCLK) drive the phase comparator, and HCLK only

provides the highest-frequency clock – if this frequency is above the maximum VCO frequency.

The pixel clock source is selected by programming bits 0 and 1 of the control register. The pixel clock

selected can then be passed through a prescaler to divide the clock by between 1 and 8. This is done by

programming CONREG[4:2]. See Chapter 16.

SCLCK

In addition to the pixel clock inputs, there is one other clock input, SCLK.

The sound system can be clocked from the internal 32-MHz IOCK32 or a 16-MHz SCLK (there is a divide-

by-2 in the sound system). The digital sound system can run at a different frequency (low MHz range);

this must be applied directly to SCLK.

NOTE: Any unused clock pin should be tied low.

236

June 1997

ADVANCE DATA BOOK v2.0

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