CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.28 VIDMUX (0x6C) — Video LCD and Serial Sound MUX Control
76543210
XXXXX X IL
This register has two functions:
Bit 1
allows selection of the type of serial sound interface to be supported.
The timing of the two possibilities is shown in the Chapter 13.
Bit 0
controls the color LCD multiplexer used with the video pixel clock to double the
available bandwidth of color LCD data provided.
Further details of how to use this feature can be found in the video and sound macrocell chapters.
L
color LCD support MUX control
I
Serial Sound Format selection
Write
bit[0]
0
1
ESEL[0] = EREG[0]
ESEL[0] = ECLK
bit[1]
0
1
normal format
Japanese format
Read
return above value
Reset
set to ‘0’ (normal)
10.3.29 IRQSTD (0x70) — IRQ D Interrupts Status
76543210
XXX 2 1 ATR
The IRQD control registers are used in an identical way to the IRQB and C registers.
2
nEVENT2, reads back high during an active-low wakeup event 2
1
nEVENT1, reads back high during an active-low wakeup event 1
A
A-to-D, active-high
T
mouse transmit active-high
R
mouse receive active-high
Write
ignored
Read
status
bits[7:5] unused
bits[4:0]
0
inactive
1
active
June 1997
ADVANCE DATA BOOK v2.0
91
MEMORY AND I/O PROGRAMMERS’ MODEL