CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.45 ATODSR (0xE4) — A-to-D Status

76543210

RRRRSSSS

This register shows which of the A-to-D channels were triggered and can have their counters read to

ascertain the analog value at the input to the channel. The interrupt request status bits are generated from

the stop flags logically AND’ed with the interrupt enables from the interrupt control register.

R[3:0]

interrupt request state for channels 4–1

S[3:0]

stop flag for channels 4–1

Write

ignored

Read

bit[7:4]

0

1

not requesting

requesting

bit [3:0]

0

1

not stopped

stopped

Reset

set all ‘0’ (not requesting or stopped)

10.3.46 ATODCC (0xE8) — A-to-D Convertor Control

76543210

DDDDCCCC

The lower 4 bits of this register directly reset each of the four counters, so that the counters can be set

back to ‘0’ before a new analog to digital conversion cycle takes place. The counter starts counting as

soon as the relevant clear bit is set back to ‘0’. The discharge transistor controls causes the channel com-

parator input to be pulled firmly down to VSS, thus discharging an external capacitor and ensuring zero

volts across the capacitor until the discharge bit is programmed low again. With the system connected

conventionally, the external capacitor begins charging as soon as the discharge bit is reset. The discharge

bit should be reset at the same time as the counter clear bit for that channel to be re-enabled.

D[3:0]

discharge transistor control for channels 4–1

C[3:0]

clear counter for channels 4–1

Write

bit[7:4]

0

1

transistor off

transistor on (discharge)

bit[3:0]

0

1

clear counter

enable counter

Read

return above values

Reset

set all ‘0’ (clear counters and don't discharge)

98

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

Share Link: