CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.33 REFCR (0x8C) — Refresh Period

76543210

XXXXRRRR

This register programs the DRAM refresh period. It is set to the fastest available rate during reset, as

refresh continues during reset to ensure that the requirements of DRAM specification can be fully met.

R

refresh period

Write

bit[3:0]

0000

0001

0010

0100

1000

refresh off

16 µs

32 µs

64 µs

128 µs

all others are undefined

Read

return the above values

Reset

set to ‘0001’ (fastest available refresh rate)

10.3.34 ID0 (0x94) — Chip ID Number (Low Byte)

76543210

0 1 1 1 1 1 00

The ID registers and the version register read back the CL-PS7500FE ID and version numbers. These

registers are read-only and must not be written to, as they are used to set the CL-PS7500FE into special

modes during production test.

Write

do not write to this location

Read

low byte of chip ID: 0x7C

10.3.35 ID1 (0x98) — Chip ID Number (High Byte)

76543210

1 0 1010 1 0

Write

Read

do not write to this location

high byte of chip ID: 0xAA

10.3.36 VERSION (0x9C) — Chip Version Number

Write

ignored

Read

chip version number byte

10.3.37 MSEDAT (0xA8) — Mouse Data

The Mouse Data and Control registers are identical to the keyboard data and control registers, and are

written to and read from in exactly the same way.

94

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

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