CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.32 ROMCR1:0 (0x80 and 0x84) — ROM Control

76543210

WS H B B N N N

The ROM interface is very flexible, allowing the length of non sequential and burst cycles to be pro-

grammed. These two registers allow this programming to take place.

The half-speed select bit is included so the interface can be used with slow ROMs when fast DRAM is

being used, and the memory system clock is running at a higher frequency. When the half-speed bit is set

low, CL-PS7500FE doubles the length of all the timings and allows the ROM interface to function correctly

with slower ROMs. In normal operation with sufficiently fast ROM devices, this bit should be programmed

to ‘1’.

Each register also contains a bit (6) that, when set, allows a 16-bit wide ROM device to be used for that

bank, by performing two 16-bit fetches to form the 32-bit word required by the CL-PS7500FE. Bit 7 allows

writes to occur to this address space; the data is driven out, and a write enable generated, if enabled.

N

B

H

S

W

Write

Read

Reset

non-sequential access time (H = 1)

000 7 MEMCLK cycles

001 6 MEMCLK cycles

010 5 MEMCLK cycles

011 4 MEMCLK cycles

100 3 MEMCLK cycles

101 2 MEMCLK cycles

burst mode access time (H = 1)

00 Burst Off

01 4 MEMCLK cycles

10 3 MEMCLK cycles

11 2 MEMCLK cycles

half-speed select, that is, double the above delays when H = 0.

Normally, the H bit should be programmed to ‘1’ (normal speed)

16- or 32-bit mode

Write Enable

bit[7]

0

1

writing disabled

writing enabled

bit[6]

0

1

32-bit

16-bit

bit[5]

0

1

half-speed mode

normal speed

return the above values

set to 0x40, that is, the 16-bit, slowest access time, to ensure all systems can

be booted from reset.

June 1997

ADVANCE DATA BOOK v2.0

93

MEMORY AND I/O PROGRAMMERS’ MODEL

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