CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.41 ASTCR (0xCC) — I/O Asynchronous Timing Control

76543210

AXXXXXXX

This register is used where I/O is being used with a very fast memory system clock. Normally it is pro-

grammed to ‘0’ to give the minimum delay for these cycles; however, in some configurations it may be nec-

essary to program the register bit to ‘1’ to slow down the internal synchronization between I/O clocks and

memory clocks and thus ensure sufficient address hold time for the I/O address.

A

asynchronous timing control

0

minimal delay to I/O cycles

1

wait states to ensure address hold time

10.3.42 DRAMCR (0xD0) — DRAM Control

76543210

XPRESSSS

This register selects between 16- and 32-bit modes of operation for each of the four available banks of

DRAM. Each bank can be individually selected for 16 or 32-bit operation. This allows a mixed 16/32-bit-

wide system to be built. It also controls EDO support and some timing options.

P

RAS precharge time

0

3 memory clock cycles guaranteed RAS precharge

1

4 memory clock cycles guaranteed RAS precharge

R

RAS-to-CAS delay on read cycles

0

2 memory clock cycles from falling nRAS to falling nCAS

1

3 memory clock cycles from falling nRAS to falling nCAS

E

EDO memory

0

Fast Page memory

1

EDO memory

S

16- or 32-bit mode select, one for each bank

Write

bit 3, bank 3 DRAM width

0

32-bit

1

16-bit

bit 2, bank 2 DRAM width

0

32-bit

1

16-bit

bit 1, bank 1 DRAM width

0

32-bit

1

16-bit

bit 0, bank 0 DRAM width

0

32-bit

1

16-bit

Read

reads above values

Reset

set bits to ‘0’ (32-bit)

96

MEMORY AND I/O PROGRAMMERS’ MODEL

ADVANCE DATA BOOK v2.0

June 1997

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