ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout
Pin
2C10A Pad
2C12A Pad 2C/2T15A/B Pad 2T26A Pad OR2T40A/B Pad Function
B1
PL1D
C2
PL1C
C1
PL1B
S D2
PL1A
D3
PL2D
D1
PL2C
E E2
PL2B
E4
—
IC E3
PL2A
E1
PL3D
D F2
—
G4
PL3C
V E F3
—
F1
PL3B
E G2
—
U G1
—
G3
PL3A
D IN H2
PL4D
J4
PL4C
H1
PL4B
T H3
PL4A
T J2
PL5D
J1
PL5C
C N K2
PL5B
J3
PL5A
E K1
PL6D
O K4
PL6C
L2
PL6B
L K3
PL6A
E C L1
PL7D
M2
PL7C
S IS M1
PL7B
L3
PL7A
N2
PL8D
D M4
PL8C
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
PL12D
PL12C
PL1D
PL1A
PL2D
PL2A
PL3D
PL3A
PL4D
PL4B
PL4A
VDD5
PL5C
PL5B
PL6D
PL7D
PL7C
PL7B
PL8D
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
PL15D
PL15C
I/O
I/O
I/O
I/O
I/O-A0
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A1
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
I/O
I/O
N1
PL8B
PL9B
PL10B
PL12B
PL15B
I/O
M3
PL8A
PL9A
PL10A
PL12A
PL15A
I/O-A7
P2
PL9D
PL10D
PL11D
PL13D
PL16D
I/O
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
108
Lattice Semiconductor