OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
Pin
2C10A Pad
2C12A Pad 2C/2T15A/B Pad 2T26A Pad OR2T40A/B Pad Function
N24
PR7A
M26
PR7B
L25
PR7C
S M24
PR7D
L26
PR6A
E M23
PR6B
K25
PR6C
L24
PR6D
IC K26
PR5A
D K23
PR5B
J25
PR5C
K24
PR5D
V E J26
PR4A
H25
PR4B
E H26
PR4C
U J24
PR4D
G25
PR3A
D IN H23
PR3B
G26
—
H24
PR3C
T F25
PR3D
T G23
—
F26
—
C N G24
—
E25
PR2A
E E26
PR2B
O F24
—
L D25
PR2C
E23
PR2D
E C D26
PR1A
E24
PR1B
S IS C25
PR1C
D24
PR1D
C26
RD_CFGN
D A25
PT16D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
—
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT18D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT20D
PR11A
PR11D
PR10A
PR10D
PR9A
PR9D
PR8A
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
RD_CFGN
PT24D
VDD5
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR7A
PR7C
PR6A
VDD5
PR5B
PR5C
PR5D
PR4A
PR4B
PR4D
PR3A
PR3D
PR2A
PR2D
PR1A
PR1D
RD_CFGN
PT30D
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-RD
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD_CFGN
I/O
B24
PT16C
PT18C
PT20C
PT24C
PT30A
I/O
A24
—
—
PT20B
PT24B
PT29B
I/O
B23
PT16B
PT18B
PT20A
PT24A
PT29A
I/O
C23
PT16A
PT18A
PT19D
PT23D
PT28D
I/O
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
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