OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
Pin
2C10A Pad
2C12A Pad 2C/2T15A/B Pad 2T26A Pad OR2T40A/B Pad Function
A23
PT15D
B22
PT15C
S D22
PT15B
C22
PT15A
E A22
PT14D
B21
PT14C
D20
PT14B
IC C21
PT14A
A21
PT13D
D B20
—
A20
PT13C
V E C20
—
B19
PT13B
E D18
—
U A19
PT13A
C19
—
D IN B18
PT12D
A18
PT12C
B17
PT12B
T C18
PT12A
T A17
PT11D
D17
PT11C
C N B16
PT11B
C17
PT11A
E A16
PT10D
O B15
PT10C
A15
PT10B
L C16
PT10A
E C B14
PT9D
D15
PT9C
S IS A14
PT9B
C15
PT9A
B13
PT8D
D D13
PT8C
PT17D
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT19A
PT18D
PT18C
PT18A
PT17D
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT23A
PT22D
PT22C
PT22A
PT21D
PT21C
PT21B
PT21A
PT20D
PT20C
PT20B
PT20A
PT19D
PT19C
PT19B
PT19A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
PT16D
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT28A
PT27D
PT27C
PT27A
PT26D
PT26C
PT26B
PT26A
PT25D
PT25C
PT25B
PT25A
VDD5
PT24C
PT24B
PT23D
PT22D
PT22A
PT21D
PT21A
PT20D
PT20A
PT19D
PT19A
PT18D
PT18A
PT17D
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
I/O-RDY/
RCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
I/O
I/O
I/O
I/O-D3
I/O
I/O
A13
PT8B
PT9B
PT10B
PT12B
VDD5
I/O-VDD5
C14
PT8A
PT9A
PT10A
PT12A
PT15A
I/O-D2
B12
PT7D
PT8D
PT9D
PT11D
PT14D
I/O-D1
C13
PT7C
PT8C
PT9C
PT11A
PT14A
I/O
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
114
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