OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
| |||
ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
Pin
2C10A Pad
2C12A Pad 2C/2T15A/B Pad 2T26A Pad OR2T40A/B Pad Function
AE3
AF3
AE4
S AD4
AF4
E AE5
AC5
AD5
IC AF5
D AE6
AC7
AD6
V E AF6
AE7
E AF7
U AD7
AE8
D IN AC9
AF8
AD8
T AE9
T AF9
AE10
C N AD9
AF10
E AC10
O AE11
L AD10
AF11
E C AE12
AF12
S IS AD11
AE13
AC12
D AF13
—
PB1B
PB1C
PB1D
PB2A
—
PB2B
—
PB2C
PB2D
PB3A
PB3B
—
PB3C
—
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
—
PB1B
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12B
PB12C
PB1B
PB2A
PB2D
PB3A
VDD5
PB4A
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7D
PB8A
PB8D
PB9A
PB9D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
PB14A
PB14D
PB15A
PB15B
PB15C
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD12
PB8D
PB9D
PB10D
PB12D
PB15D
I/O
AE14
PB9A
PB10A
PB11A
PB13A
PB16A
I/O
AC14
PB9B
PB10B
PB11B
PB13B
PB16B
I/O
AF14
PB9C
PB10C
PB11C
PB13C
PB16C
I/O
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
110
Lattice Semiconductor
Share Link: 