OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C10A, OR2C12A, OR2C/2T15A/B, OR2T26A, and OR2T40A/B 352-Pin PBGA
Pinout (continued)
Pin
2C10A Pad
2C12A Pad 2C/2T15A/B Pad 2T26A Pad OR2T40A/B Pad Function
A12
PT7B
PT8B
PT9B
PT10D
PT13D
I/O
B11
PT7A
PT8A
PT9A
PT10A
PT13A
I/O-D0/DIN
C12
PT6D
PT7D
PT8D
PT9D
PT12D
I/O
S A11
PT6C
PT7C
PT8C
PT9A
PT12A
I/O
D12
PT6B
PT7B
PT8B
PT8D
PT11D
I/O
E B10
PT6A
PT7A
PT8A
PT8A/
PT11A
I/O-DOUT
C11
PT5D
PT6D
PT7D
PT7D
PT10D
I/O
A10
PT5C
PT6C
PT7C
PT7C
PT10A
I/O
IC D10
PT5B
PT6B
PT7B
PT7B
PT9D
I/O
D B9
PT5A
PT6A
PT7A
PT7A
PT9A
I/O
C10
PT4D
PT5D
PT6D
PT6D
PT8D
I/O
A9
PT4C
PT5C
PT6C
PT6C
PT8A
I/O
V E B8
PT4B
PT5B
PT6B
PT6B
PT7D
I/O
A8
PT4A
PT5A
PT6A
PT6A
PT7A
I/O-TDI
E C9
—
PT4D
PT5D
PT5D
PT6D
I/O
U B7
PT3D
PT4C
PT5C
PT5C
PT6C
I/O
D8
—
PT4B
PT5B
PT5B
PT6B
I/O
D IN A7
PT3C
PT4A
PT5A
PT5A
VDD5
I/O-VDD5
C8
—
PT3D
PT4D
PT4D
PT5D
I/O
B6
PT3B
PT3C
PT4C
PT4C
PT5C
I/O
T D7
—
PT3B
PT4B
PT4B
PT5B
I/O
T A6
PT3A
PT3A
PT4A
PT4A
PT5A
I/O-TMS
C7
PT2D
PT2D
PT3D
PT3D
PT4D
I/O
C N B5
PT2C
PT2C
PT3A
PT3A
PT4A
I/O
A5
PT2B
PT2B
PT2D
PT2D
PT3D
I/O
E C6
—
—
PT2C
PT2C
PT3C
I/O
O B4
—
—
PT2B
PT2B
PT3B
I/O
L D5
PT2A
PT2A
PT2A
PT2A
PT3A
I/O
A4
PT1D
PT1D
PT1D
PT1D
PT2D
I/O
E C C5
PT1C
PT1C
PT1C
PT1C
PT2A
I/O
B3
PT1B
PT1B
PT1B
PT1B
PT1D
I/O
S IS C4
PT1A
PT1A
PT1A
PT1A
PT1A
I/O-TCK
A3 RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/
TDO
D A1
VSS
VSS
VSS
VSS
VSS
VSS
A2
VSS
VSS
VSS
VSS
VSS
VSS
A26
VSS
VSS
VSS
VSS
VSS
VSS
AC13
VSS
VSS
VSS
VSS
VSS
VSS
AC18
VSS
VSS
VSS
VSS
VSS
VSS
AC23
VSS
VSS
VSS
VSS
VSS
VSS
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
115
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