OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 46B. OR2TxxB Programmable I/O Cell Timing Characteristics
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Parameter
Symbol
Speed
-7
-8
Unit
Min
Max
Min
Max
S Inputs (TJ = 85 °C, VDD = min)
Input Rise Time
TR
—
Input Fall Time
TF
—
E Pad to In Delay
PAD_IN_DEL
—
Pad to Nearest PFU Latch Output
CHIP_LATCH
—
IC Delay Added to General Routing
—
—
(input buffer in delay mode for
D OR2T15B and smaller devices)
Delay Added to General Routing
—
—
V (input buffer in delay mode for
E OR2T40B)
Delay Added to Direct-FF Routing
—
—
E (input buffer in delay mode for
U OR2T15B and smaller devices)
Delay Added to Direct-FF Routing
—
—
D (input buffer in delay mode for
IN OR2T40B)
500
—
500
ns
500
—
500
ns
1.1
—
1.0
ns
3.3
—
2.4
ns
6.6
—
6.1
ns
8.9
—
8.2
ns
6.4
—
6.0
ns
8.7
—
8.0
ns
Outputs (TJ = 85 °C, VDD = min, CL = 50 pF)
PFU CK to Pad Delay (DOUT[3:0] to
T PAD):
T Fast
DOUT_DEL(F)
—
Slewlim
DOUT_DEL(SL)
—
Sinklim
DOUT_DEL(SI)
—
C N Output to Pad Delay (OUT[3:0] to
PAD):
Fast
OUT_DEL(F)
—
E Slewlim
OUT_DEL(SL)
—
Sinklim
OUT_DEL(SI)
—
O 3-state Enable Delay (TS[3:0] to
PAD):
L Fast
TS_DEL(F)
—
Slewlim
TS_DEL(SL)
—
E C Sinklim
TS_DEL(SI)
—
2.8
—
2.5
ns
3.6
—
3.3
ns
8.3
—
8.0
ns
2.8
—
2.5
ns
3.6
—
3.3
ns
8.3
—
8.0
ns
3.0
—
2.7
ns
3.8
—
3.4
ns
9.1
—
8.7
ns
Notes:
If the input buffer is placed in delay mode, the chip hold time to the nearest PFU latch is guaranteed to be 0 if the clock is routed using the
S IS primary clock network; (TJ = all, VDD = all). It should also be noted that any signals routed on the clock lines or using the TRIDI buffers directly
from the input buffer do not get delayed at any time.
D The delays for all input buffers assume an input rise/fall time of ≤1 V/ns.
Lattice Semiconductor
159
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