OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Timing Characteristics (continued)
Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
D[7:0] Setup Time
TS
20
S D[7:0] Hold Time
TH
0
CCLK High Time
TCH
50
CCLK Low Time
TCL
50
E CCLK Frequency
FC
—
CCLK to DOUT
TD
—
IC Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Max
—
—
—
—
10
30
Unit
ns
ns
ns
ns
MHz
ns
D Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics
V E OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
E D[7:0] Setup Time
TS
15
U D[7:0] Hold Time
TH
0
CCLK High Time
TCH
12.5
D IN CCLK LowTime
TCL
12.5
CCLK Frequency
FC
—
CCLK to DOUT
TD
—
Max
—
—
—
—
40
10
Unit
ns
ns
ns
ns
MHz
ns
T T Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
EC N CCLK
L O INIT
TINIT_CLK
E C D[7:0]
S IS DOUT
D RDY
BYTE 0
TCH
TCL
TH
TS
BYTE 1
TD
0
1
2
3
4
5
6
7
0
5-4534(F)
Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram
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