OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 47. Series 2 General Configuration Mode Timing Characteristics (continued)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
Slave Parallel Mode
S Power-on Reset Delay
CCLK Period (OR2CxxA/OR2TxxA)
CCLK Period (OR2TxxB)
E Configuration Latency (noncompressed):
OR2C/2T04A
OR2C/2T06A
IC OR2C/2T08A
D OR2C/2T10A
OR2C12A
OR2C/2T15A
V E OR2T15B
OR2C/2T26A
OR2C/2T40A
E U OR2T40B
Partial Reconfiguration (noncompressed):
OR2C/2T04A
D IN OR2C/2T06A
OR2C/2T08A
OR2C/2T10A
T OR2C12A
T OR2C/2T15A/2T15B
OR2C/2T26A
C OR2C/2T40A/2T40B
N INIT Timing
INIT High to CCLK Delay:
E Slave Parallel
O Slave Serial
L Synchronous Peripheral
Master Serial:
E C (M3 = 1)
(M3 = 0)
Master Parallel:
S IS (M3=1)
(M3 = 0)
Initialization Latency (PRGM high to INIT high):
D OR2C/2T04A
Symbol
TPO
TCCLK
TCCLK
TCL
TPR
TINIT_CLK
TIL
Min
4.33
100.00
25.0
0.82
1.14
1.44
1.86
2.25
2.76
0.69
3.84
5.93
1.48
1.70
2.00
2.20
2.50
2.70
3.00
3.50
4.30
Max
17.37
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.00
1.00
1.00
1.06
0.59
5.28
1.12
63.36
—
—
—
4.51
2.65
21.47
4.77
254.40
Unit
ms
ns
ns
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs
µs
µs
µs
µs
µs
µs
µs
OR2C/2T06A
74.98
301.04
µs
OR2C/2T08A
86.59
347.68
µs
OR2C/2T10A
98.21
394.32
µs
OR2C12A
109.82
440.96
µs
OR2C/2T15A/2T15B
121.44
487.60
µs
OR2C/2T26A
144.67
580.88
µs
OR2C/2T40A/2T40B
181.90
730.34
µs
INIT High to WR, Asynchronous Peripheral
TINIT_WR
1.50
—
µs
Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR2CxxA and between 2.7 V and 3.0 V for the OR2TxxA/OR2TxxB.
Lattice Semiconductor
161
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