OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 50. Series 2 Asynchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Min
WR, CS0, and CS1 Pulse Width
TWR
100
S D[7:0] Setup Time
TS
20
D[7:0] Hold Time
TH
0
E RDY Delay
TRDY
—
RDY Low
TB
1
Earliest WR After RDY Goes High*
TWR2
0
IC RD to D7 Enable/Disable
TDEN
—
D CCLK to DOUT
TD
—
Max
—
—
—
60
8
—
60
30
* This parameter is valid whether the end of not RDY is determined from the RDY/RCLK pin or from the D7 pin.
V E Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input D[7:0].
E D[6:0] timing is the same as the write data port of the D7 waveform because D[6:0] are not enabled.
Unit
ns
ns
ns
ns
CCLK Periods
ns
ns
ns
D U CS0
IN CS1
T T WR
EC N D7
EL CO RD
TWR
TS
TH
WRITE DATA
TWR2
TDEN
TDEN
S DIS RDY
TB
TRDY
CCLK
TD
DOUT
PREVIOUS BYTE
D7
D0
D1
D2
D3
5-4533.a
Figure 68. Asynchronous Peripheral Configuration Mode Timing Diagram
Lattice Semiconductor
165
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