ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

13. AXI Matrix (AXIMX)

13.1

Description

The AXI Matrix comprises the embedded Advanced Extensible Interface (AXI) bus protocol which supports

separate address/control and data phases, unaligned data transfers using byte strobes, burst-based transactions

with only start address issued, separate read and write data channels to enable low-cost DMA, ability to issue

multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to

provide timing closure.

13.2

Embedded Characteristics

 High performance AXI network interconnect

 2 Masters:

̶ Core

̶ AHB/AXI bridge from AHB Matrix

 3 Slaves:

̶ ROM

̶ AXI/AHB bridge to AHB Matrix

̶ Slave0 of MPDDRC

 Single-cycle arbitration

 Full pipelining to prevent master stalls

 1 remap state

13.3 Operation

13.3.1 Remap

Remap states are managed in the AXI Matrix Remap Register (AXIMX_REMAP): AXIMX_REMAP.REMAP0

(register bit 0) is used to remap RAM @ addr 0x00000000.

Refer to Section 13.4 “AXI Matrix (AXIMX) User Interface”.

The number of remap states can be defined using eight bits of the AXIMX_REMAP register, and a bit in

AXIMX_REMAP controls each remap state.

Each remap state can be used to control the address decoding for one or more slave interfaces. If a slave interface

is affected by two remap states that are both asserted, the remap state with the lowest remap bit number takes

precedence.

Each slave interface can be configured independently so that a remap state can perform different functions for

different masters.

A remap state can:

 Alias a memory region into two different address ranges

 Move an address region

 Remove an address region

Because of the nature of the distributed register subsystem, the masters receive the updated remap bit states in

sequence, and not simultaneously.

A slave interface does not update to the latest remap bit setting until:

 The address completion handshake accepts any transaction that is pending

 Any current lock sequence completes

At powerup, ROM is seen at address 0. After powerup, the internal SRAM can be moved down to address 0 by

means of the remap bits.

82 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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