ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

14.8.1 Arbitration Scheduling

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst

breaking as well as to provide the maximum throughput for slave interfaces, arbitration may only take place during

the following cycles:

1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently

accessing it.

2. Single Cycles: When a slave is currently doing a single access.

3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst,

predicted end of burst matches the size of the transfer but is managed differently for undefined length burst.

“See “Undefined Length Burst Arbitration”.

4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master

access is too long and must be broken. See “Slot Cycle Limit Arbitration”.

14.8.1.1 Undefined Length Burst Arbitration

In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the

user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be

selected from the following Undefined Length Burst Type (ULBT) possibilities:

 Unlimited: no predetermined end of burst is generated. This value enables 1 Kbyte burst lengths.

 1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.

 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR

transfer.

 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR

transfer.

 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR

transfer.

 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR

transfer.

 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR

transfer.

 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR

transfer.

The use of undefined length 8-beat bursts, or less, is discouraged since this may decrease the overall bus

bandwidth due to arbitration and slave latencies at each first access of a burst.

However, if the usual length of undefined length bursts is known for a master it is recommended to configure the

ULBT accordingly.

This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).

14.8.1.2 Slot Cycle Limit Arbitration

The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g.,

an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in

the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock

cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access

cycle.

Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a

badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled

(SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by

some Atmel masters.

SAMA5D3 Series [DATASHEET]

89

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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