ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATSAMA5D35A-CU Datasheet PDF : 1917 Pages
| |||
To change from one type of default master to another, the Bus Matrix user interface provides the Slave
Configuration Registers, one for every slave, that set a default master for each slave. The Slave Configuration
Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects
the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR
field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section
14.10.2 “Bus Matrix Slave Configuration Registers” on page 96.
14.5
No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle in between,
or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever the number of requesting masters.
14.6
Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.
This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non
privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful
for masters that mainly perform single accesses or short bursts with some Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever is the number of requesting masters.
14.7
Fixed Default Master
After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave.
All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-
privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single
accesses or short bursts with Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput, regardless of the number of requesting masters.
14.8
Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e., when two
or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus
arbitrating each slave specifically.
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for
each slave:
1. Round-robin Arbitration (default)
2. Fixed Priority Arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
When re-arbitration must be done, specific conditions apply. See Section 14.8.1 “Arbitration Scheduling” on page
89.
88 SAMA5D3 Series [DATASHEET]
Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16
Share Link: 