ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

In most cases, this feature is not needed and should be disabled for power saving.

Warning: This feature cannot prevent any slave from locking its access indefinitely.

14.8.2 Arbitration Priority Scheme

The bus Matrix arbitration scheme is organized in priority pools corresponding each to an access criticality class as

shown in the corresponding “Latency Quality of Service” column in Table 14-4. When the Latency Quality of

Service is enabled for a master-slave pair through the Bus Matrix, the priority pool to use for arbitration at the slave

port is determined from the master. When the Latency Quality of Service is disabled, it is determined through the

Bus Matrix user interface. See Section 14.10.3 “Bus Matrix Priority Registers A For Slaves” on page 97.

After reset, the Latency Quality of Service is enabled by default on all of the master ports that are connected to a

master driving the Latency Quality of Service signals, as shown in the bit “LQOSENx: Latency Quality of Service

Enable for Master x” of Section 14.10.3 “Bus Matrix Priority Registers A For Slaves” on page 97 and Section

14.10.4 “Bus Matrix Priority Registers B For Slaves” on page 98.

Table 14-4. Arbitration Priority Pools

Priority pool

Latency Quality of Service

3

Latency Critical

2

Latency Sensitive

1

Bandwidth Sensitive

0

Background Transfers

Round-robin priority is used in the highest and lowest priority pools 3 and 0, whereas fixed level priority is used

between priority pools and in the intermediate priority pools 2 and 1.

For each slave, each master is assigned to one of the slave priority pools thanks to the Latency Quality of Service

inputs or to the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating

master requests, this priority pool level always takes precedence.

After reset, most of the masters belong to the lowest priority pool (MxPR = 0, Background Transfer) and are

therefore granted bus access in a true round-robin order.

The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than

one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight

and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring

high-priority master request will be granted after the current bus master access has ended and other high priority

pool master requests, if any, have been granted once each.

The lowest priority pool shares the remaining bus bandwidth between AHB Masters.

Intermediate priority pools allow fine priority tuning. Typically, a latency-sensitive master or a bandwidth-sensitive

master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority.

For good CPU performance, it is recommended to let the CPU priority configured with the default reset value 2

(Latency Sensitive).

All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be

assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with

no master for intermediate fix priority levels.

14.8.2.1 Fixed Priority Arbitration

Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct

priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority

pools).

90 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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