ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

14. Bus Matrix (MATRIX)

14.1

Description

The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths

between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix

interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is

one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The

Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides 16 Special Function

Registers (MATRIX_SFR) that allow the Bus Matrix to support application specific features.

14.1.1 Matrix Masters

The Bus Matrix of the SAMA5D3 manages 15 masters, which means that each master can perform an access

concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for

each master. In order to simplify the addressing, all the masters have the same decodings.

Table 14-1. List of Bus Matrix Masters

Master No. Description

0

Cortex A5

1, 2, 3 DMA Controller 0

4, 5, 6 DMA Controller 1

7

GMAC DMA

8, 9

LCDC DMA

10

UHP EHCI DMA

11

UHP OHCI DMA

12

UDPHS DMA

13

EMAC DMA

14

ISI DMA

14.1.2 Matrix Slaves

The Bus Matrix of the SAMA5D3 manages 13 slaves. Each slave has its own arbiter, allowing a different

arbitration per slave.

Table 14-2. List of Bus Matrix Slaves

Slave No. Description

0

Internal SRAM0

1

Internal SRAM1

2

NFC SRAM

3

Internal ROM

4

Soft Modem (SMD)

USB Device High Speed Dual Port RAM (DPR)

5

USB Host OHCI registers

USB Host EHCI registers

6

External Bus Interface/NFC

7

DDR2 Port0

SAMA5D3 Series [DATASHEET]

85

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

Share Link: