ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

14.2

Embedded Characteristics

 AMBA Advanced High-performance Bus (AHB Lite) Compliant Interfaces

 32- or 64-bit Data Bus

 APB Compliant User Interface

 Configurable Number of Masters (Up to sixteen)

 Configurable Number of Slaves (Up to sixteen)

 One Decoder for Each Master

 Several Possible Boot Memories for Each Master before Remap

 One Remap Function for Each Master

 Support for Long Bursts of 32, 64, 128 and Up to the 256-beat Word Burst AHB Limit

 Enhanced Programmable Mixed Arbitration for Each Slave

̶ Round-Robin

̶ Fixed Priority

̶ Latency Quality of Service

 Programmable Default Master for Each Slave

̶ No Default Master

̶ Last Accessed Default Master

̶ Fixed Default Master

 Deterministic Maximum Access Latency for Masters

 Zero or One Cycle Arbitration Latency for the First Access of a Burst

 Bus Lock Forwarding to Slaves

 Master Number Forwarding to Slaves

 One Special Function Register for Each Slave (Not dedicated)

 Register Write Protection Write Protection of User Interface Registers

14.3

Memory Mapping

The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master

several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address

while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.

The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR) that performs the

remap action for every master independently.

14.4

Special Bus Granting Mechanism

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from

masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is

free from any other master access. It does not provide any benefit if the slave is continuously accessed by more

than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access

latency.

This bus granting mechanism sets a different default master for every slave.

At the end of the current access, if no other request is pending, the slave remains connected to its associated

default master. A slave can be associated with three kinds of default masters:

 no default master

 last access master

 fixed default master

SAMA5D3 Series [DATASHEET]

87

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

Share Link: