ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

Serial Peripheral Interface (SPI) Port—Master Timing

Table 37 and Figure 26 describe SPI port master operations.

Table 37. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Timing Requirements

tSSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

tHSPIDM

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tSDSCIM

tSPICHM

tSPICLM

tSPICLK

tHDSM

tSPITDM

tDDSPIDM

tHDSPIDM

SPISELx low to First SCK Edge

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCK Edge to SPISELx High

Sequential Transfer Delay

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

VDDEXT

1.8V Nominal

Min

Max

11.6

–1.5

2 × tSCLK – 1.5

2 × tSCLK – 1.5

2 × tSCLK – 1.5

4 × tSCLK

2 × tSCLK – 1.5

2 × tSCLK– 1.5

6

–1

VDDEXT

2.5 V/3.3V Nominal

Min

Max

Unit

9.6

ns

–1.5

ns

2 × tSCLK – 1.5

ns

2 × tSCLK – 1.5

ns

2 × tSCLK – 1.5

ns

4 × tSCLK

ns

2 × tSCLK – 1.5

ns

2 × tSCLK – 1.5

ns

6

ns

–1

ns

SPIxSELy

(OUTPUT)

SPIxSCK

(OUTPUT)

tSDSCIM

tSPICLM

tSPICHM

tSPICLK

tHDSM

tSPITDM

SPIxMOSI

(OUTPUT)

CPHA = 1

SPIxMISO

(INPUT)

tHDSPIDM

tDDSPIDM

tSSPIDM

tHSPIDM

SPIxMOSI

(OUTPUT)

CPHA = 0

tSSPIDM

SPIxMISO

(INPUT)

tHSPIDM

tHDSPIDM

tDDSPIDM

Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. D | Page 43 of 68 | April 2014

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