ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF516KSWZ-3 Datasheet PDF : 68 Pages
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ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Up/Down Counter/Rotary Encoder Timing
Table 42. Up/Down Counter/Rotary Encoder Timing
VDDEXT
1.8V Nominal
Parameter
Min Max
Timing Requirements
tWCOUNT
tCIS
tCIH
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low1
Counter Input Hold Time After CLKOUT Low1
tSCLK + 1
9
0
1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
tSCLK + 1
ns
7
ns
0
ns
CLKOUT
CUD/CDG/CZM
tCIS
tCIH
tWCOUNT
Figure 31. Up/Down Counter/Rotary Encoder Timing
10/100 Ethernet MAC Controller Timing
Table 43 through Table 48 and Figure 32 through Figure 37
describe the 10/100 Ethernet MAC Controller operations.
Table 43. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter1
Timing Requirements
tERXCLKF
tERXCLKW
tERXCLKIS
tERXCLKIH
ERxCLK Frequency (fSCLK = SCLK Frequency)
ERxCLK Width (tERxCLK = ERxCLK Period)
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
VDDEXT
1.8V Nominal
Min
Max
None
tERxCLK × 40%
7.5
7.5
25 + 1%
tERxCLK × 60%
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
None
tERxCLK × 35%
7.5
7.5
25 + 1%
tERxCLK × 65%
MHz
ns
ns
ns
ERx_CLK
ERxD3–0
ERxDV
ERxER
tERXCLKW
tERXCLK
tERXCLKIS tERXCLKIH
Figure 32. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Rev. D | Page 47 of 68 | April 2014
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