ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 38 and Figure 27 describe SPI port slave operations.

Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Timing Requirements

tSPICHS

Serial Clock High Period

tSPICLS

Serial Clock Low Period

tSPICLK

Serial Clock Period

tHDS

Last SCK Edge to SPISS Not Asserted

tSPITDS

Sequential Transfer Delay

tSDSCI

SPISS Assertion to First SCK Edge

tSSPID

Data Input Valid to SCK Edge (Data Input Setup)

tHSPID

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tDSOE

tDSDHI

tDDSPID

tHDSPID

SPISS Assertion to Data Out Active

SPISS Deassertion to Data High Impedance

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

VDDEXT

1.8V Nominal

Min

Max

2 × tSCLK –1.5

2 × tSCLK –1.5

4 × tSCLK –1.5

2 × tSCLK – 1.5

2 × tSCLK – 1.5

2 × tSCLK –1.5

1.6

2

0

12

0

11

10

0

VDDEXT

2.5 V/3.3V Nominal

Min

Max

Unit

2 × tSCLK –1.5

ns

2 × tSCLK –1.5

ns

4 × tSCLK –1.5

ns

2 × tSCLK – 1.5

ns

2 × tSCLK – 1.5

ns

2 × tSCLK –1.5

ns

1.6

ns

1.6

ns

0

10.3

ns

0

9

ns

10

ns

0

ns

SPIxSS

(INPUT)

SPIxSCK

(INPUT)

SPIxMISO

(OUTPUT)

CPHA = 1

SPIxMOSI

(INPUT)

tSDSCI

tSPICLS

tSPICHS

tDSOE

tDDSPID

tHDSPID

tSSPID

tHSPID

tDSOE

SPIxMISO

(OUTPUT)

CPHA = 0

SPIxMOSI

(INPUT)

tHDSPID

tSPICLK

tDDSPID

tHDS

tSPITDS

tDSDHI

tDDSPID

tSSPID

tDSDHI

tHSPID

Figure 27. Serial Peripheral Interface (SPI) Port—Slave Timing

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

The UART ports receive and transmit operations are described

in the ADSP-BF51x Hardware Reference Manual.

Rev. D | Page 44 of 68 | April 2014

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