QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
R
CLK
D
Q
E
tISU
tIHL
tICO
tIRST
tIESU
tIEH
Figure 15: Input Register Cell
Table 15: Standard Input Delays
Symbol
Parameter
Standard Input Delays
To get the total input delay add this delay to tISU
tSID(LVTTL)
tSID(LVCMOS2)
LVTTL input delay: Low Voltage TTL for 3.3V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower
applications
tSID(GTL+)
tSID(SSTL3)
tSID(SSTL2)
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3V
SSTL2 input delay: Stub Series Terminated Logic for 2.5V
Value
Min Max
- 0.34 ns
- 0.42 ns
- 0.68 ns
- 0.55 ns
- 0.61 ns
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