R
CLK
D
Q
E
QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
tISU
tIHL
tICO
tIRST
tIESU
tIEH
Figure 16: Input Register Cell Timing
Quad net
Figure 17: Global Clock Structure
Clock
Logic Cells (Internal)
I/O’s (External)
Table 16: Eclipse Clock Performance
Parameters
Clock Performance
Global
Dedicated
Clock signal generated internally 1.51 ns (max)
1.59 ns (max)
Clock signal generated externally 2.06 ns (max)
1.73 ns (max)
© 2003 QuickLogic Corporation
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