QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL5732-33BPS484M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

Table 17: QL5732 Global Clock Performance

Clock Segment

Parameter

Value

Min

Max

tPGCK

Global clock pin delay to quad net

-

tBGCK

Global clock buffer delay (quad net

to flip flop)

-

1.34 ns

0.56 ns

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

tPGCK

tBGCK

Figure 18: Global Clock Structure Schematic

Symbol

tOUTLH

tOUTHL

tPZH

tPZL

tPHZ

tPLZ

tCOP

Table 18: Output Register Cell

Parameter: Output Register Cell Only

Output Delay low to high (90% of H)

Output Delay high to low (10% of L)

Output Delay tri-state to high (90% of H)

Output Delay tri-state to low (10% of L)

Output Delay high to tri-State

Output Delay low to tri-State

Clock to out delay (does not include clock tree delays)

Min

Max

-

0.40

-

0.55

-

2.94

-

2.34

-

3.07

-

2.53

3.15 (fast slew)

-

10.2 (slow

slew)

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© 2003 QuickLogic Corporation

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