QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL5732-33BPS484M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

Table 20: Output Slew Rates @ VCCIO = 2.5 V

Fast Slew

Slow Slew

Rising Edge

1.7 V/ns

0.6 V/ns

Falling Edge

1.9 V/ns

0.6 V/ns

1K Ohms

tPHZ

5pF

1K Ohms

tPLZ

5pF

Figure 21: Loads for tPXZ

Pin Type Descriptions

The QL5732 Device Pins are indicated in Table 21. Some of the pins presented in this table

connect to the PCI bus, and others are programmable as user I/O.

Table 21: Pin Descriptions

Pin

Function

Description

TDI/RSI

Test Data In for JTAG /RAM

init. Serial Data In

TRSTB/RRO

Active low Reset for JTAG

/RAM init. reset out

Hold HIGH during normal operation. Connects to serial PROM

data in for RAM initialization. Connect to VCC if unused

Hold LOW during normal operation. Connects to serial PROM

reset for RAM initialization. Connect to GND if unused

TMS

Test Mode Select for JTAG

Hold HIGH during normal operation. Connect to VCC if not used

for JTAG

TCK

Test Clock for JTAG

Hold HIGH or LOW during normal operation. Connect to VCC or

ground if not used for JTAG

TDO/RCO

Test data out for JTAG /RAM

init. clock out

Connect to serial PROM clock for RAM initialization. Must be left

unconnected if not used for JTAG or RAM initialization

I/GCLK

High-drive input and/or global

clock network driver

Can be configured as either input or global clock

I/O

Input/Output pin

Can be configured as an input and/or output

VCC

VCCIO<PCI>

Power supply pin

Input voltage tolerance pin

VCCIO<A>-<E> Input voltage tolerance pin

Connect to 2.5 V supply

Connect to 3.3 V supply

Connect to 3.3 V supply if 3.3 V input tolerance is required;

otherwise, connect to 2.5 V supply

GND

Ground pin

Connect to ground

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