QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
Manufacturer
QL5732-33BPS484M
QuickLogic Corporation
QL5732-33BPS484M Datasheet PDF : 41 Pages
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QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
Pin
PLLIN
DEDCLK
GNDPLL
INREF
PLLOUT
IOCTRL
Table 21: Pin Descriptions
Function
Description
PLL clock input
Clock input for PLL
Dedicated clock pin
Low skew global clock
Ground pin for PLL
Connect to GND
Differential reference voltage
Connect to reference voltage or ground if used for non-differential
input
PLL output pin
Dedicated PLL output pin. Otherwise may be left unconnected
Highdrive input
Can be used as highdrive input or clock to I/O register within the
same bank. Tied low or high if unused
Recommended Unused Pin Terminations
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally
using the Configuration Editor. This option is given in the bottom-right corner of the placement
window. To use the Placement Editor, choose ConstraintÆFix Placement in the Option pull-
down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in Table 22.
Signal Name
PLLOUT<x>
IOCTRL<y>
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
Table 22: Recommended Unused Pin Terminations
Recommended Termination
Unused PLL output pins must be connected to either VCC or GND so that their
associated input buffer never floats. Utilized PLL output pins that route the PLL clock
outside of the chip should not be tied to either VCC or GND.
Any unused pins of this type must be connected to either VCC or GND.
Any unused clock pins should be connected to VCC or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to
VCC; under normal operation, use it as needed.
If an I/O bank does not require the use of INREF signal the pin should be connected
to GND.
NOTE: x -> number, y -> alphabetical character.
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