FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
Notes:
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
for the UART 2 logical device, by setting the DMA Enable bit. Refer to the IRCC specification.
DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Section 19.2.7 - Note A. Logical
Device IRQ and DMA Operation.
19.2.7 Note A. Logical Device IRQ and DMA Operation
1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a
register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the IRQ
and DACK disabled by the Configuration Registers (active bit or address not valid).
a. FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high
impedance). Will not respond to the DREQ
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
b. Serial Port 1 and 2:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port
interrupt is forced to a high impedance state - disabled.
c. Parallel Port:
i. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled (high
impedance).
ii. ECP Mode:
(1) (DMA) dmaEn from ecr register. See table.
(2) IRQ - See table.
MODE
IRQ PIN
PDREQ PIN
(FROM ECR REGISTER)
CONTROLLED BY CONTROLLED BY
000
PRINTER
IRQE
dmaEn
001
SPP
IRQE
dmaEn
010
FIFO
(on)
dmaEn
011
ECP
(on)
dmaEn
100
EPP
IRQE
dmaEn
101
RES
IRQE
dmaEn
110
TEST
(on)
dmaEn
111
CONFIG
IRQE
dmaEn
d. Keyboard Controller: Refer to the KBD section of this spec.
19.2.8 SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration
Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or
the RESET_DRV signal. These registers are not affected by soft resets.
SMSC FDC37C672
Page 132
DATASHEET
Rev. 10-29-03
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